The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

Aug. 18, 2023
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

En-Shou Tang, Hsinchu, TW;

Yuan-Chun Lin, Hsinchu, TW;

Kai-Hsiang Chang, Hsinchu, TW;

Yi-Che Tsai, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 12/1027 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 13/1689 (2013.01);
Abstract

A memory processing system includes a processor, a main memory, and a MMU coupled to the processor and the main memory. The processor is used to generate a plurality of virtual addresses. The main memory includes a plurality of data corresponding to physical addresses in a main page table. The main page table is used to map the plurality of virtual addresses to the plurality of physical addresses. The memory management unit includes a TLB coupled to the processor and the main memory, a table walk unit coupled to the TLB and the main memory, and a merger coupled to the TLB and the processor. The TLB performs address translation by retrieving a physical address according to a virtual address from a first page table in the TLB or a second page table in the table walk unit or the main page table in the main memory.


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