The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2025

Filed:

May. 24, 2024
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Lorenzo Di Gregorio, Munich, DE;

Andrew David Tune, Dronfield, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 11/34 (2006.01); G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/0864 (2016.01); G06F 12/0875 (2016.01); G06F 12/0888 (2016.01); G06F 12/1009 (2016.01); G06F 12/0802 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0888 (2013.01); G06F 11/3471 (2013.01); G06F 12/08 (2013.01); G06F 12/0811 (2013.01); G06F 12/0864 (2013.01); G06F 12/0875 (2013.01); G06F 12/1009 (2013.01); G06F 12/0802 (2013.01);
Abstract

A control circuit is configured to receive a stream of addresses associated with cache lookup requests resulting from execution of a workload by a data processing system. The control circuit includes a cache miss monitor and a cache hit monitor both coupled to a controller. The cache miss monitor determines a number of reoccurring misses as a difference between the number of addresses in the stream of addresses that miss in the cache and the number of such addresses that are unique. The cache hit monitor includes a moment circuit configured to determine first and second frequency moments addresses in the stream of addresses that hit in the cache. The controller controls the data processing system based on the number of reoccurring misses and the first and second frequency moments. A bypass mechanism of the cache may be controlled, for example.


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