The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Apr. 26, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Junhyun Lee, Yongin-si, KR;

Dong-Ho Kim, Yongin-si, KR;

Haegoo Jung, Yongin-si, KR;

Jooho Lim, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/40 (2025.01); H01L 25/16 (2023.01); H10D 86/60 (2025.01); H10H 20/857 (2025.01); H10K 59/12 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H10H 20/857 (2025.01); H01L 25/167 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

A display device includes: a substrate including a display area and a non-display area positioned around the display area and including a pad area adjacent to one side of the display area, a light emitting element disposed in the display area on the substrate, a pad portion disposed in the pad area on the substrate and including a plurality of output pads, a driving chip, and a control signal line. The driving chip includes a base portion facing the substrate, overlapping the pad area, and including dummy bump areas, an output bump area positioned between the dummy bump areas, and a data output area positioned between the dummy bump areas, a plurality of dummy bumps attached to a lower surface of the base portion and overlapping the dummy bump areas and the output bump area, respectively, a plurality of output bumps attached to the lower surface of the base portion, overlapping the output bump area, and connected in parallel to each other through transistors, and a plurality of detection bumps attached to the lower surface of the base portion, each of the detection bumps is electrically connected to the output bumps and overlapping the output bump area. The control signal line electrically connected through the transistors to the output bumps.


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