The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Sep. 27, 2023
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Tomoyuki Obata, Matsumoto, JP;

Soichi Yoshida, Matsumoto, JP;

Tetsutaro Imagawa, Matsumoto, JP;

Seiji Momota, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/80 (2025.01); H10D 12/00 (2025.01); H10D 62/13 (2025.01); H10D 84/60 (2025.01);
U.S. Cl.
CPC ...
H10D 84/811 (2025.01); H10D 12/211 (2025.01); H10D 62/133 (2025.01); H10D 84/617 (2025.01);
Abstract

Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.


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