The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Mar. 07, 2022
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02); H10D 30/0413 (2025.01); H10D 30/0415 (2025.01); H10D 30/693 (2025.01); H10D 30/694 (2025.01); H10D 30/701 (2025.01); H10D 62/151 (2025.01); H10D 64/033 (2025.01); H10D 64/037 (2025.01); H10D 64/689 (2025.01);
Abstract

A NOR-type storage device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The NOR-type storage device includes: a gate stack extending vertically on a substrate; an active region surrounding a periphery of the gate stack, the active region including first and second source/drain regions, a first channel region between the first and second source/drain regions, third and fourth source/drain regions, and a second channel region between the third and fourth source/drain regions; first, second, third and fourth interconnection layers extending laterally from the first to fourth source/drain regions, respectively; and a source line contact part extending vertically with respect to the substrate to pass through the first to fourth interconnection layers and electrically connected to one of the first interconnection layer and the second interconnection layer, and to one of the third interconnection layer and the fourth interconnection layer.


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