The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Oct. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Namkyu Cho, Suwon-si, KR;

Seokhoon Kim, Suwon-si, KR;

Jeongho Yoo, Suwon-si, KR;

Choeun Lee, Suwon-si, KR;

Pankwi Park, Suwon-si, KR;

Dongsuk Shin, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); B82Y 10/00 (2011.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/40 (2025.01); H10D 62/822 (2025.01); H10D 62/832 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/01 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 64/259 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 62/121 (2025.01);
Abstract

A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.


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