The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

May. 02, 2023
Applicant:

Analog Power Conversion Llc, Bend, OR (US);

Inventors:

Dumitru G. Sdrulla, Bend, OR (US);

Amaury Gendron-Hansen, Bend, OR (US);

Wang-Chang A. Gu, Bend, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/00 (2025.01); H01L 23/373 (2006.01); H01L 23/528 (2006.01); H10D 12/01 (2025.01); H10D 62/832 (2025.01); H10D 64/64 (2025.01);
U.S. Cl.
CPC ...
H10D 30/202 (2025.01); H01L 23/3736 (2013.01); H01L 23/5286 (2013.01); H10D 12/031 (2025.01); H10D 62/8325 (2025.01); H10D 64/64 (2025.01);
Abstract

A silicon carbide (SiC) static induction transistor (SIT) includes a source, a gate disposed over the source and receiving a control signal, a drain disposed over the recessed gate and generating an output signal, an epitaxial pattern disposed between the source and the drain and including a protruding portion, and a gate bus electrically coupled to the gate and including carbon. A method of forming an SiC SIT transistor device includes providing a substrate including a source doped with dopants of a first conductivity type, forming an epitaxial pattern including a protruding portion over the source, forming a recessed gate over the source, forming a gate bus over the recessed gate, forming a drain over the gate bus and the epitaxial pattern, and forming a first heatsink over the drain.


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