The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
May. 21, 2020
Applicant:
Mitsubishi Electric Corporation, Tokyo, JP;
Inventors:
Kentaro Yoshida, Tokyo, JP;
Koichiro Kisu, Tokyo, JP;
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 12/00 (2025.01); H01L 23/00 (2006.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 12/411 (2025.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 2224/3201 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/3303 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13055 (2013.01); H10D 64/231 (2025.01);
Abstract
The semiconductor device according to the present disclosure has features (1) to (3) below. The feature (1) is that 'a lower surface of an on-chip bonding material has a shape matching a surface shape of a main current wiring connection region in plan view'. The feature (2) is that “an emitter sense wiring is directly connected to a side surface of the main current wiring connection region”. The feature (3) is that “an IGBT chip has an ineffective region in which the IGBT does not function in a region below an emitter sense pad and the emitter sense wiring”.