The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jul. 05, 2022
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10B 51/40 (2023.02); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Disclosed are a NOR-type memory device and an electronic apparatus. The NOR-type memory device includes a NOR cell array and a peripheral circuit. The NOR cell array includes: a first substrate; an array of memory cells on the first substrate, wherein each memory cell includes a first gate stack extending vertically with respect to the first substrate and an active region surrounding a periphery of the first gate stack; first bonding pads electrically connected to the first gate stacks; and second bonding pads electrically connected to the active regions. The peripheral circuit includes: a second substrate; peripheral circuit elements on the second substrate; and third bonding pads, wherein at least some of the third bonding pads are electrically connected to the peripheral circuit elements. At least some of the first bonding pads and the second bonding pads are opposite to at least some of the third bonding pads.


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