The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Apr. 07, 2023
Samsung Electronics Co., Ltd., Suwon-si, KR;
Byongju Kim, Suwon-si, KR;
Dongsung Choi, Suwon-si, KR;
Wonjun Park, Suwon-si, KR;
Donghwa Lee, Suwon-si, KR;
Jaemin Jung, Suwon-si, KR;
Changheon Cheon, Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.