The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Nov. 25, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Keunnam Kim, Suwon-si, KR;

Kiseok Lee, Suwon-si, KR;

Byeongjoo Ku, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/40 (2023.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10B 41/40 (2023.02); H01L 23/5283 (2013.01); H10B 12/50 (2023.02); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02); H10D 86/201 (2025.01);
Abstract

A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.


Find Patent Forward Citations

Loading…