The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Oct. 26, 2022
Imec Vzw, Leuven, BE;
Shanghaitech University, Shanghai, CN;
Xinzhe Liu, Shanghai, CN;
Raees Kizhakkumkara Muhamad, Uccle, BE;
Dessislava Nikolova, Borsbeek, BE;
Yajun Ha, Shanghai, CN;
Francky Catthoor, Temse, BE;
Fupeng Chen, Shanghai, CN;
Peter Schelkens, Willebroek, BE;
David Blinder, Antwerp, BE;
Imec vzw, Leuven, BE;
ShanghaiTech University, Shanghai, CN;
Abstract
Example embodiments relate to methods for disseminating scaling information and applications thereof in very large scale integration (VLSI) implementations of fixed-point fast Fourier transforms (FFTs). One embodiment includes a method for disseminating scaling information in a system. The system includes a linear decomposable transformation process and an inverse process of the linear decomposable transformation process. The inverse process of the linear decomposable transformation process is defined, in time or space, as an inverse linear decomposable transformation process. The linear decomposable transformation process is separated from the inverse linear decomposable transformation process. The linear decomposable transformation process or the inverse linear decomposable transformation process is able to be performed first and is defined as a linear decomposable transformation I. The other remaining process is performed subsequently and is defined as a linear decomposable transformation II. The method for disseminating scaling information is used for a bit width-optimized and energy-saving hardware implementation.