The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jul. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sreedhar Ravipalli, Cupertino, CA (US);

Jing Miao, Livermore, CA (US);

Raghucharan Boddupalli, Bangalore, IN;

Luan Bui, San Jose, CA (US);

Dinesh Kotti, Saratoga, CA (US);

Ranjini Rajeevan, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H03K 19/17704 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17744 (2013.01); H03K 19/17708 (2013.01);
Abstract

Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.


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