The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Sep. 08, 2023
Shure Acquisition Holdings, Inc., Niles, IL (US);
Eugen Warkentin, Elgin, IL (US);
Mack Mansouri, Wheeling, IL (US);
Shure Acquisition Holdings, Inc., Niles, IL (US);
Abstract
An adjustable clock that may be implemented on a field-programmable gate array (FPGA). The adjustable clock may be highly accurate and stable, and may be adjustable in response to software commands. The adjustable clock may be configured to generate a clock signal that is synchronized in frequency and/or phase with a clock that is external to the FPGA, such as a Precision Time Protocol (PTP) clock. The FPGA may implement the adjustable clock with a number of elements as programmable logic, including a numerically-controlled frequency divider, a multi-tap delay line, logic configured to dynamically select, for each clock pulse, a delay of the multi-tap delay line, and a feedback loop to control the numerically-controlled frequency divider.