The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jul. 13, 2023
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Masato Miyamoto, Yokkaichi, JP;

Hiroyuki Ogawa, Yokkaichi, JP;

Tomohiro Kubo, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); G11C 16/0483 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures including a vertical channel and memory elements located in the memory openings, a contact via cavity vertically extending through the alternating stack, and an integrated contact-and-support assembly located in the contact via cavity. The integrated contact-and-support assembly includes a dielectric support pillar and a conductive layer contact via structure electrically contacting a top surface of a first electrically conductive layer of the electrically conductive layers that surrounds the contact via cavity. A dielectric spacer is located in the contact via cavity, covering a sidewall of the first electrically conductive layer in the contact via cavity, and extending above the top surface of the first electrically conductive layer.


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