The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jul. 26, 2024
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Jang Mi Kang, Yongin-si, KR;

Jun Hyun Park, Yongin-si, KR;

Min Jae Jeong, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H10K 59/121 (2023.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); G09G 2300/0413 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/0257 (2013.01); G09G 2330/021 (2013.01);
Abstract

A pixel of display device includes a light emitting element, a first transistor coupled between first power source and a second node and having a gate electrode connected to a first node N, and the first transistor being configured to control a driving current supplied to the light emitting element in response to a voltage of the first node, a first capacitor including one electrode connected to the first node and another electrode connected to a third node, a second transistor coupled between the third node and a data line, a third transistor coupled between the first node and the second node, a fourth transistor coupled between the first node and an initialization power source, a fifth transistor coupled between a reference power source and the third node, and an eighth transistor coupled between a fourth node and an anode initialization power source.


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