Memory devices performing selective post package repair, electronic devices including the same, and operating methods of the same

Abstract

Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips, in response to a post package repair (PPR) command and a target value received from a controller, performs a write operation of write data with respect to memory cells corresponding to a row address generated in a PPR mode executed in response to the PPR command, performs read operation with respect to the memory cells, resulting in read data, generates a comparison signal based on a result of comparing the write data and the read data programs the row address corresponding to the comparison signal as a selected fail row address, and writes the write data in redundancy memory cells, which are connected to a redundancy word line used to replace a fail word line corresponding to the selected fail row address, from among the plurality of memory cells.