Deserializer and memory module including the same

Abstract

A deserializer includes a shift register circuit that outputs N output data by shifting input data based on a first clock signal, a clock divider that outputs N second clock signals N-divided from the first clock signal and having N phases different from each other, and outputs one or more third clock signal divided to have a frequency less than that of the second clock signals, a clock selecting circuit that outputs a selected clock signal having an edge corresponding to a second time after N number of clock cycles of the first clock signal have elapsed from a first time at which a valid period is detected in a selection signal for selecting the input data based on the N second clock signals and the one or more third clock signals, and a data align circuit that parallelizes the N output data based on the selected clock signal.