The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Dec. 08, 2023
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Ming-Cheng Lo, New Taipei, TW;
Shih-Chang Huang, Hsinchu, TW;
Jui-Chun Chang, Hsinchu, TW;
Wu-Hsi Lu, Hsinchu, TW;
Yu-Che Tsai, Hsinchu, TW;
Shih-Hao Liu, Taoyuan, TW;
Yen-Shih Ho, Taoyuan, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
A method of fabricating a semiconductor device includes providing a substrate that includes a handle substrate, a bottom cladding layer, and a semiconductor layer stacked in sequence from bottom to top. The substrate includes an electronic integrated circuit (EIC) region and a photonic integrated circuit (PIC) region. A thermal oxidation process is performed on the semiconductor layer in the PIC region to form an oxide layer. A first thickness of the semiconductor layer in the EIC region is greater than a second thickness of the semiconductor layer below the oxide layer. The oxide layer is removed and a PIC structure is formed on the bottom cladding layer in the PIC region. An EIC structure is formed on the bottom cladding layer in the EIC region. An interconnect structure is formed to be electrically connected to the PIC and EIC structures.