The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

May. 16, 2022
Applicant:

Fraunhofer-gesellschaft Zur Förderung Der Angewandten Forschung E.v., Munich, DE;

Inventors:

Bernd Richter, Dresden, DE;

Philipp Wartenberg, Dresden, DE;

Stephan Brenner, Dresden, DE;

Volker Kirchhoff, Wehlen, DE;

Uwe Vogel, Dresden, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01); H10K 59/82 (2023.01);
U.S. Cl.
CPC ...
H10K 59/121 (2023.02); H10D 86/0221 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10K 59/131 (2023.02); H10K 59/82 (2023.02);
Abstract

Provided is a semi-transparent display and a method for producing a semi-transparent display. An SOI wafer is provided, the surface having at least one pixel region and at least one contact region arranged next to the pixel region, the SOI wafer comprising a silicon substrate on the rear side. At least one electromagnetic-radiation-emitting layer is deposited on the front side of the SOI wafer. At least one transparent cover layer is applied above the at least one electromagnetic-radiation-emitting layer. A wiring carrier is fastened to the assembly comprising the SOI wafer, the electromagnetic-radiation-emitting layer and the transparent cover layer. Before fastening of the wiring carrier to the assembly, the silicon substrate is removed from the assembly, producing a residual assembly, and electrically conductive connections are formed between the contact region of the SOI wafer and the wiring carrier from the rear side of the SOI wafer.


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