The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Mar. 02, 2023
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Teruyuki Ohashi, Kawasaki Kanagawa, JP;

Hiroshi Kono, Himeji Hyogo, JP;

Shunsuke Asaba, Himeji Hyogo, JP;

Takahiro Ogata, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/832 (2025.01); H10D 8/60 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/8325 (2025.01); H10D 8/60 (2025.01); H10D 62/106 (2025.01); H10D 64/519 (2025.01); H10D 64/62 (2025.01); H10D 84/146 (2025.01);
Abstract

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes a first silicon carbide region of n-type having a first portion in contact with a first plane, a second silicon carbide region of p-type, a third silicon carbide region of n-type, and a gate electrode. The diode region includes the first silicon carbide region of n-type having a second portion in contact with the first plane and a fourth silicon carbide region of p-type. The semiconductor device includes a gate wiring electrically connected to the gate electrode. A distance between a high-concentration portion included in the fourth silicon carbide region and the gate wiring is larger than a distance between a high-concentration portion included in the second silicon carbide region and the gate wiring.


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