The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jul. 12, 2023
Applicant:

Marvell Israel (M.i.s.l) Ltd., Yokneam, IL;

Inventors:

Liav Ben Artsi, Nahariya, IL;

Ram Ben Ezra, Yokneam Illit, IL;

Assignee:

Marvell Asia Pte Ltd, Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0218 (2013.01); H05K 1/115 (2013.01); H05K 3/4038 (2013.01); H05K 2201/10734 (2013.01);
Abstract

An electrical circuit board assembly includes: (I) a surface, having a plurality of terminals disposed thereon for transferring a power signal to an electronic device, (II) at least first and second layers separated by at least one dielectric layer, the first and second layers being configured to (a) be connected to the power signal, and (b) electrically conduct at least a portion of the power signal, and (III) multiple vias that (i) mechanically traverse the first and second layers at respective traversal points, and (ii) are electrically connected to the terminals on the surface, the multiple vias including: first vias that, at the respective traversal points, are electrically connected to the first layer and electrically isolated from the second layer, and second vias that, at the respective traversal points, are electrically connected to the second layer and electrically isolated from the first layer.


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