The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jul. 03, 2023
Applicant:

Novatek Microelectronics Corp., Hsinchu, TW;

Inventors:

Ying-Cheng Lin, Taoyuan, TW;

Che-Yi Lin, Hsinchu, TW;

Chun-Po Huang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/02 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H04L 25/0294 (2013.01); H03F 3/45645 (2013.01); H04L 25/0276 (2013.01);
Abstract

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.


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