The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

May. 28, 2020
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

David Alexander Macquistan, Ottawa, CA;

Kelvin Prosyk, Luskville, CA;

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/32 (2006.01); H01L 21/02 (2006.01); H01S 5/10 (2021.01); H01S 5/22 (2006.01); H10F 71/00 (2025.01);
U.S. Cl.
CPC ...
H01S 5/3202 (2013.01); H01L 21/02293 (2013.01); H01L 21/02392 (2013.01); H01S 5/1003 (2013.01); H01S 5/2206 (2013.01); H10F 71/00 (2025.01);
Abstract

A method includes obtaining a semiconductor wafer having an orientation in a plane; depositing one or more masks to a semiconductor wafer, wherein each mask is configured to cover a portion of the semiconductor wafer, and wherein each mask includes a perimeter having multiple sides that are substantially aligned along a preferred crystal direction relative to the orientation that provides reduced or enhanced growth enhancement at edges of the substantially aligned sides; and performing Selective Area Epitaxy (SAE) growth on a surface of the semiconductor wafer, wherein the one or more masks inhibit the SAE growth over the associated portion.


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