The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Feb. 14, 2023
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Satoshi Yoshida, Kanagawa, JP;

Tatsunori Sakano, Tokyo, JP;

Ryohei Gejo, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/492 (2013.01); H01L 23/498 (2013.01); H01L 23/5226 (2013.01); H01L 24/29 (2013.01); H01L 25/072 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/2918 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/13055 (2013.01);
Abstract

According to one embodiment, a semiconductor package includes a first conductive member, a second conductive member, a plurality of semiconductor devices, a wiring member, a first connection member, and a second connection member. The plurality of semiconductor devices is provided between the first conductive member and the second conductive member. One of the semiconductor devices includes a semiconductor member, a first electrode, a first control electrode, a second control electrode, and a second electrode. The first and second conductive members are electrically connected to the first and second electrodes, respectively. The wiring member includes first, second and third wiring layers, and an insulating region. A part of the insulating region is located between the first wiring layer and the third wiring layer, and between the third wiring layer and the second wiring layer. The second wiring layer includes a first connection region and a second connection region.


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