The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

May. 22, 2024
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventors:

Keisuke Fujishiro, Sagamihara, JP;

Yoshifumi Mochida, Sagamihara, JP;

Assignee:

Lodestar Licensing Group LLC, Evanston, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 8/12 (2013.01);
Abstract

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.


Find Patent Forward Citations

Loading…