The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2025
Filed:
Nov. 28, 2023
Tsinghua University, Beijing, CN;
Wenjun Tang, Beijing, CN;
Xueqing Li, Beijing, CN;
Weihang Long, Beijing, CN;
Jialong Liu, Beijing, CN;
Yilun Zhong, Beijing, CN;
Chen Jiang, Beijing, CN;
Huazhong Yang, Beijing, CN;
TSINGHUA UNIVERSITY, Beijing, CN;
Abstract
The present disclosure relates to a sensing-memory-computing synergy device, chip and electronic device. The said device comprises: at least one sensing-memory-computing synergy cell, wherein each sensing-memory-computing synergy cell comprises K sensing elements, where the first end of each sensing element is connected to wordline, the second end of each sensing element is connected to bitline, the sensing element can sense changes in external inputs, and K is an integer greater than or equal to zero; a control module which controls the voltages of each wordline and bitline so that the sensing-memory-computing synergy cell can perform desired operations, and sense the voltage or current on bitlines to obtain the operation results. The present embodiment of the disclosure implements the sensing-memory-computing synergy cell by sensing elements, which combines sensing and in-memory computing. The sensing elements gather sensor data from external inputs, and the sensing-memory-computing synergy operation is performed by controlling the voltages on wordlines and bitlines. The present embodiment of the disclosure enables the in-situ sensing, memory and computing functions in a device with decreased wiring and control complexity, which lowers the computing latency and improves robustness and energy efficiency.