The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

May. 31, 2022
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jingwen Zhang, Beijing, CN;

Miao Wang, Beijing, CN;

Tiaomei Zhang, Beijing, CN;

Yunsheng Xiao, Beijing, CN;

Haigang Qing, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01);
Abstract

A pixel circuit includes a driving sub-circuit coupled to a first node, a second node and a third node, a compensation sub-circuit coupled to the first node, the third node and a first scan signal terminal, an adjustment sub-circuit, and a writing sub-circuit. The compensation sub-circuit includes a first transistor group, and the first transistor group includes at least two first transistors connected in series. A fourth node is formed between a second electrode of a first first transistor and a first electrode of a second first transistor. The adjustment sub-circuit is coupled to the fourth node and at least one control terminal. The adjustment sub-circuit is configured to, in light-emitting phases, adjust a voltage of the fourth node under a control of a signal from the at least one control terminal, so as to reduce a voltage difference between the fourth node and the first node.


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