The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Nov. 18, 2022
Applicant:

Verifai Inc., Palo Alto, CA (US);

Inventors:

William Alexander Hughes, San Jose, CA (US);

Sandeep Srinivasan, Palo Alto, CA (US);

Rohit Uday Suvarna, Jersey City, NJ (US);

Assignee:

VERIFAI INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2023.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/08 (2013.01); G06N 20/00 (2019.01);
Abstract

Methods, systems, and devices for tuning a set of simulation parameters associated with a design verification environment are described that include: simulating a circuit design according to a set of simulation runs; providing, to a machine learning network, an indication of functional coverage results associated with simulating the circuit design according to the set of simulation runs; receiving an output in response to the machine learning network processing the functional coverage results; and simulating the circuit design based on a recommended set of simulation parameters. The output includes: an indication of a near miss event associated with the functional coverage results; and the recommended set of simulation parameters. Simulating the circuit design based on the recommended set of simulation parameters includes generating a set of component signals associated with triggering the near miss event.


Find Patent Forward Citations

Hughes, William. (2025). Method and system for using deep learning to improve design verification by optimizing code coverage, functional coverage, and bug detection (U.S. Patent No. 12468874). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12468874

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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