The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jun. 13, 2024
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Gaurav Garg, San Jose, CA (US);

Bernard J. Semeria, Palo Alto, CA (US);

James Vash, San Ramon, CA (US);

Jeff Gonion, Campbell, CA (US);

Richard F. Russo, San Jose, CA (US);

Peter A. Lisherness, Los Gatos, CA (US);

Roy G. Moss, Palo Alto, CA (US);

Rohit K. Gupta, Santa Clara, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 12/1027 (2013.01); G06F 2212/68 (2013.01); G06F 2213/28 (2013.01);
Abstract

Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.


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