The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jan. 23, 2024
Applicant:

Arista Networks, Inc., Santa Clara, CA (US);

Inventors:

John Peach, London, GB;

Harold Wang, Santa Clara, CA (US);

Martin Hull, Santa Clara, CA (US);

Assignee:

Arista Networks, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/32 (2006.01); G08B 5/38 (2006.01);
U.S. Cl.
CPC ...
G06F 11/325 (2013.01); G08B 5/38 (2013.01);
Abstract

A flash definition specifying a flashing sequence for a status indicator of a multi-lane port is stored on a device. In operation, the status indicator is lit, following the flashing sequence, to indicate a current lane state (in a Port/Lane Signaling Mode) or interface/channel state (in an Interface/Channel Signaling Mode). The flashing sequence may begin with a preamble, indicating a start of the flashing sequence. The device may have different multi-lane ports, each having one or more status indicators configured for indicating states of multiple lanes or a state of an interface having a multiple of component lanes. Flashing sequences for these ports are synchronizable (to the port having the largest number of lanes or, in the Interface/Channel Signaling Mode, the largest number of configured interfaces on that port). The lanes of a multi-lane port may operate at the same or different speeds and may be bundled into interfaces/channels.


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