The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2025

Filed:

Jun. 22, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Sagar Koorapati, Austin, TX (US);

Manu Gulati, Saratoga, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/26 (2013.01);
Abstract

A throttle management circuit is configured to receive throttle request(s) from at least one state detection circuit, generate and store a throttle recommendation in each clock cycle based on the received throttle request(s), and generate a throttle control signal to throttle activity of processing circuits based on a recent and stored throttle recommendation. The throttle requests may be based on measures of electric states, thermal states, and/or activity states among the processing circuits monitored by the LAM circuit and the measured states may be caused by activity of the processing circuits. The throttle management circuit can provide a local, dynamic, low-latency response to mitigate harm that could otherwise be caused by the measured local states of the processing circuits while waiting for a response from the power management hierarchy. In some examples, the throttle recommendation generated in each cycle affects the throttle control signal for a plurality of subsequent cycles.


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