The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Sep. 07, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joongsuk Oh, Hwaseong-si, KR;

Jaeung Koo, Seoul, KR;

Boun Yoon, Seoul, KR;

Ilyoung Yoon, Hwaseong-si, KR;

Kangchun Lee, Suwon-si, KR;

Seungjae Lee, Seoul, KR;

Junhwan Yim, Seoul, KR;

Huiteak Hong, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01);
Abstract

A semiconductor device manufacturing method is capable of manufacturing a semiconductor device with improved reliability, by simplifying a chemical mechanical polishing (CMP) process and minimizing a thickness distribution of a dummy gate during the CMP process. The semiconductor device manufacturing method includes forming, on a substrate, dummy gate structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each dummy gate structure including a dummy gate and a mask pattern on an upper surface of the dummy gate; forming an interlayer insulating layer covering the dummy gate structures; and performing the single slurry CMP process of removing some of the interlayer insulating layer and the dummy gate structures through the single slurry CMP process and exposing the upper surface of the dummy gate.


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