The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Mar. 22, 2021
Applicant:

Azur Space Solar Power Gmbh, Heilbronn, DE;

Inventors:

Thorsten Wierzkowski, Heilbronn, DE;

Daniel Fuhrmann, Heilbronn, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 62/60 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 8/422 (2025.01); H10D 8/043 (2025.01); H10D 62/60 (2025.01); H10D 62/85 (2025.01);
Abstract

A stacked high-blocking III-V semiconductor power diode and manufacturing method, wherein the III-V semiconductor power diode comprises a first highly doped semiconductor contact area, a low-doped semiconductor drift region disposed beneath the first semiconductor contact area, a highly doped second semiconductor contact area disposed beneath the semiconductor drift region, and two terminal contact layers, at least the first semiconductor contact area forms a core stack, the core stack is surrounded by a dielectric frame region along the side face, the upper surface or lower surface of the core stack and the dielectric frame region terminate with each other or form a step with respect to each other, and semiconductor areas of the III-V semiconductor power diode arranged beneath the first semiconductor contact area are each either surrounded by the core stack or form a carrier portion.


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