The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Apr. 28, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jae Young Oh, Icheon-si, KR;

Joong Gyu Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 23/5283 (2013.01); H10B 41/27 (2023.02);
Abstract

A semiconductor memory device includes a plurality of conductive patterns and a plurality of second interlayer insulating layers arranged alternately with each other under a first interlayer insulating layer. The semiconductor memory device also includes a doped semiconductor layer including an amorphous area overlapping the first interlayer insulating layer and a crystalline area overlapping the first interlayer insulating layer with the amorphous area interposed between the first interlayer insulating layer and the crystalline area. The semiconductor memory device further includes a channel layer contacting the doped semiconductor layer and passing through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns. The semiconductor memory device additionally includes a memory layer between each of the conductive patterns and the channel layer.


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