The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

May. 02, 2024
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Edward Lee, Fullerton, CA (US);

Ravi Ananth, Laguna Niguel, CA (US);

Michael Chapman, Long Beach, CA (US);

Marco Palma, Castagneto Po, IT;

Michael A. De Rooij, Playa Vista, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/10 (2006.01); H03K 17/06 (2006.01); H03K 17/30 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 17/102 (2013.01); H03K 17/063 (2013.01); H03K 17/302 (2013.01); H03K 19/01855 (2013.01);
Abstract

A circuit for synchronizing the turn-on/turn-off times of parallel FETs. The circuit includes a plurality of integrated circuits and a synchronizer. Each of the integrated circuits includes a power FET which operates in parallel with the power FETs of the other integrated circuits, and a phase detector. The phase detector receives and compares the phase output signal of the integrated circuit with the phase output signal of another integrated circuit, and provides signals to the synchronizer regarding the relative turn-on times of the power FETs based upon the phase output signals. The synchronizer, in response to the signals from each of the integrated circuits, reduces or increases the turn-on times of the power FETs, thereby synchronizing the turn-on times of the power FETs.


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