The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

May. 15, 2023
Applicants:

Icp Technology Co., Ltd., Taoyuan, TW;

Sentec Green Energy Technology Co., Ltd., Taoyuan, TW;

Inventors:

Ho-Chieh Yu, Taoyuan, TW;

Chen-Cheng-Lung Liao, Taoyuan, TW;

Chun-Yu Lin, Taoyuan, TW;

Jason An Cheng Huang, Taoyuan, TW;

Chih-Chuan Liang, Taoyuan, TW;

Kun-Tzu Chen, Taoyuan, TW;

Nai-His Hu, Taoyuan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/49838 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06155 (2013.01);
Abstract

Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 μm, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.


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