The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Sep. 01, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyeongmun Kang, Hwaseong-si, KR;

Taehyeong Kim, Suwon-si, KR;

Woodong Lee, Cheonan-si, KR;

Hwanyoung Choi, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 21/56 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/32059 (2013.01); H01L 2224/3207 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/33183 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/182 (2013.01);
Abstract

A semiconductor package includes a base structure, a lower semiconductor chip disposed on the base structure, an upper semiconductor chip disposed on the lower semiconductor chip, a connecting structure including a lower pad disposed on the lower semiconductor chip, an upper pad disposed under the upper semiconductor chip, and a connecting bump disposed between the lower pad and the upper pad, a dummy chip disposed on the upper semiconductor chip, an upper adhesive layer including an upper adhesive portion disposed between the upper semiconductor chip and the dummy chip, and an upper protrusion portion disposed at opposite sides of the upper adhesive portion, to surround lower portions of opposite side surfaces of the dummy chip, and a molding layer disposed at opposite sides of the dummy chip, to surround upper portions of the opposite side surfaces of the dummy chip and the upper protrusion portion.


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