The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Sep. 15, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Vamsi Krishna Sambangi, Vizianagaram, IN;

Sai Naresh Gajapaka, Hyderabad, IN;

Santhosh Reddy Akavaram, Hyderabad, IN;

Venkatesha M Iyengar, Bengaluru, IN;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/56 (2013.01); G06F 3/06 (2006.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 21/566 (2013.01); G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 21/79 (2013.01); G06F 2221/034 (2013.01);
Abstract

Systems and methods for improving security of a Universal Flash Storage (UFS) device during a purge operation. If a purge operation being performed in the UFS device is interrupted prematurely, due to issuance of one or more urgent commands, the UFS device notifies the host processor that the purge operation has been interrupted. After the host processor performs the urgent command(s), it causes the UFS device to resume performance of the purge operation and the host processor delays performance of any other commands that arrive at the command queue (CQ) of the host processor until the resumed purge operation has been completed. Because the purge operation is resumed and completed before the host processor performs any of the other command(s) that have arrived at the CQ, die-level attacks seeking to access unpurged data by sending read commands to the CQ of the host processor are thwarted.


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