The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2025
Filed:
Jun. 30, 2023
Advanced Micro Devices, Inc., Santa Clara, CA (US);
William Peter Ehrett, Austin, TX (US);
Anthony Gutierrez, Bellevue, WA (US);
Vedula Venkata Srikant Bharadwaj, Bellevue, WA (US);
Karthik Ramu Sangaiah, Bellevue, WA (US);
Prachi Shukla, Santa Clara, CA (US);
Sriseshan Srikanth, Austin, TX (US);
Ganesh Dasika, Austin, TX (US);
John Kalamatianos, Boxborough, MA (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.