Processor

Abstract

The processor includes core circuits and a cache unit having L2 to LN caches (N is 3 or more). L1 cache has a move-in buffer including entries in which memory access instruction resulted in cache miss in L1 cache is stored. The move-in buffer, when issuing a normal memory request to L2 cache, issues a pseudo memory request to L3 to LN caches in parallel and receives a pseudo data response that has coherency-unsecured data from any one cache. The re-order buffer executes a normal instruction execution completion process in response to the normal data response, executes a pseudo instruction execution completion process in response to the pseudo data response, and, when the pseudo data response is a failure, rewinds an arithmetic operation circuit that speculatively executed instructions after the memory access instruction in response to the pseudo instruction execution completion process, back to a state before the speculative execution.