The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Oct. 14, 2019
Applicant:

The Board of Trustees of the University of Illinois, Urbana, IL (US);

Inventors:

Nam Sung Kim, Champaign, IL (US);

Hadi Esmaeilzadeh, Atlanta, GA (US);

Amir Yazdanbakhsh, Atlanta, GA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01); G06F 1/03 (2006.01); G06F 7/527 (2006.01); G06N 3/04 (2023.01); G11C 7/10 (2006.01); G06F 17/17 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01); G06F 1/03 (2013.01); G06F 7/527 (2013.01); G06N 3/04 (2013.01); G11C 7/1012 (2013.01); G06F 17/17 (2013.01);
Abstract

A random access memory may include memory banks and arithmetic approximation units. Each arithmetic approximation unit may be dedicated to one or more of the memory banks and include a respective multiply-and-accumulate unit and a respective lookup-table unit. The respective multiply-and-accumulate unit is configured to iteratively perform shift and add operations with two inputs and to provide a result of the shift and add operations to the respective lookup-table unit. The result approximates or is a product of the two inputs. The respective lookup-table unit is configured produce an output by applying a pre-defined function to the result. The arithmetic approximation units are configured for parallel operation. The random access memory may also include a memory controller configured to receive instructions, from a processor, regarding locations within the memory banks from which to obtain the two inputs and in which to write the output.


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