The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jan. 24, 2024
Applicant:

Proteantecs Ltd., Haifa, IL;

Inventors:

Eyal Fayneh, Givatayim, IL;

Yahel David, Kibbutz Gazit, IL;

Evelyn Landman, Haifa, IL;

Assignee:

PROTEANTECS LTD., Haifa, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2856 (2013.01); G01R 31/2882 (2013.01);
Abstract

Failure risk measurement in a semiconductor Integrated Circuit (IC) by generating a pulse of a preset time duration on an output path when a signal from a data path and/or control logic circuit of the semiconductor IC changes. The data paths and/or control logic circuits of the semiconductor IC have a common clock. The output paths may be combined to provide a combined output path and a signal on the combined output path may be delayed by a configurable time duration, providing a delayed combined output path signal thereby. The delayed combined output path signal may be received at a data input of a device state element, which is clocked by a signal based on the common clock and outputs a failure risk measurement signal.


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