The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Sep. 21, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Kanta Watanabe, Yokkaichi, JP;

Yanli Zhang, San Jose, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/27 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/6891 (2025.01); H10D 30/694 (2025.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers, a vertical layer stack located over the alternating stack, and including multiple levels of vertically interlaced drain select electrodes and drain-select-level insulating layers, a first insulating layer located between the alternating stack and the vertical layer stack, the first insulating layer having a thickness which is greater than a thickness of the respective insulating layers and the respective drain-select-level insulating layers, drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures, memory openings vertically extending through the vertical layer stack, the first insulating layer, and the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective memory film.


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