The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Oct. 05, 2021
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Pieter Weckx, Bunsbeek, BE;

Assignee:

Imec vzw, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/31144 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/7684 (2013.01); H01L 21/76879 (2013.01); H01L 21/76897 (2013.01);
Abstract

A method includes: producing on a substrate a stack of: a first layer including a first dielectric material, a second layer including dielectric material on the first layer, and an etch stop layer between the first layer and the second layer, etching a trench through the second layer, the etch stop layer, and the first layer, producing a lower conductive line in the trench, producing a third layer including a second dielectric material in the trench and on the tower conductive line, removing a first portion of the second layer, such that a second portion of the second layer remains in contact with the etch stop layer, etching a via opening through the third layer in the trench, using the second portion of the second layer as a mask, and depositing a conductive upper line and an interconnect via on the lower conductive line within the via opening.


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