The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Sep. 12, 2022
Infineon Technologies Ag, Neubiberg, DE;
Marco Ludwig, Wickede, DE;
Guido Boenig, Warstein, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A power semiconductor module arrangement includes at least one substrate comprising a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; at least one semiconductor body arranged on the first metallization layer; a housing at least partly enclosing the substrate, the housing comprising sidewalls; and at least one press-on pin, wherein each press-on pin is arranged either on the substrate or on one of the at least one semiconductor body and extends from the substrate or the respective semiconductor body in a vertical direction that is perpendicular to a top surface of the substrate, and each press-on pin is mechanically coupled to at least one sidewall of the housing by means of a bar, each bar extending horizontally between the respective press-on pin and sidewall, and parallel to the top surface of the substrate.