The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Feb. 24, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ming He, San Jose, CA (US);

Jaehyun Park, Hwaseong-si, KR;

Chihak Ahn, Fremont, CA (US);

Mehdi Saremi, Danville, CA (US);

Rebecca Park, Mountain View, CA (US);

Harsono Simka, Saratoga, CA (US);

Daewon Ha, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H01L 21/76 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76283 (2013.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/015 (2025.01);
Abstract

Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.


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