The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Mar. 18, 2022
Applicant:

Chilisin Electronics Corp., Hsinchu County, TW;

Inventor:

Ming-Chieh Chiu, Taoyuan, TW;

Assignee:

CHILISIN ELECTRONICS CORP., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 5/00 (2006.01); H01F 27/24 (2006.01); H01F 27/28 (2006.01); H01F 27/32 (2006.01); H01F 41/12 (2006.01);
U.S. Cl.
CPC ...
H01F 27/2804 (2013.01); H01F 27/24 (2013.01); H01F 27/323 (2013.01); H01F 41/122 (2013.01); H01F 2027/2809 (2013.01);
Abstract

A thin film inductor is provided. The thin film inductor includes a first coil assembly, a first magnetic layer, and a second magnetic layer. The first coil assembly includes a first substrate and two first electrically conductive circuits respectively arranged on two surfaces of the first substrate that are opposite to each other. The first magnetic layer and the second magnetic layer are respectively arranged on the two surfaces of the first substrate that are opposite to each other, and the two first electrically conductive circuits are respectively embedded in the first magnetic layer and the second magnetic layer. The first substrate has a first non-circuit layout, and the first electrically conductive circuit is arranged around the first non-circuit layout. A ratio between an area of the first non-circuit layout and an area of the first substrate is 0.1 or more.


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