The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Feb. 29, 2024
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventors:
Kenrou Kikuchi, Yokohama, JP;
Yasuhiro Shimura, Yokohama, JP;
Assignee:
KIOXIA CORPORATION, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract
A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.