The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Jan. 18, 2022
Applicant:

Analog Devices, Inc., Wilmington, MA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Cheng C. Wang, San Jose, CA (US);

Assignee:

Analog Devices, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/544 (2006.01);
U.S. Cl.
CPC ...
G06F 7/5443 (2013.01);
Abstract

An integrated circuit comprising a plurality of multiplier-accumulator circuits connected in series to form a linear pipeline to process first data, via performing a plurality of concatenated multiply and accumulate operations, and generate MAC output data, wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits includes (i) a multiplier to multiply first data by a multiplier weight data and generate a product data, and (ii) an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data. The integrated circuit further includes an activation circuit, connected to the output of the linear pipeline of the plurality of multiplier-accumulator circuits, to receive the MAC output data and process the MAC output data, via a non-linear activation function, to generate MAC pipeline output data.


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